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US 2018/0322007 A1Published application
Morphable ecc encoder/decoder for nvdimm over ddr channel
AssigneeSamsung Electronics Co., Ltd.
InventorsDimin NIU, Mu-Tien CHANG, Hongzhong ZHENG
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Abstract
A hardware coding mechanism is described. The coding mechanism may include a first encoder to produce a first code using a base number of bits and a second encoder to produce a second code using a supplementary number of bits. The second code and the first code together may be stronger than the first code alone. A mode register stored in a storage may specify whether a switch to the second encoder is open or closed: the first coder is always used.
Claims20
A coding mechanism implemented in hardware, comprising:
- a first encoder to produce a first code for a data, the first code including a base number of bits;
- a second encoder to produce a second code for the data, the second code including a supplementary number of bits;
- storage for a mode register;
- and
- a switch responsive to the mode register to control whether or not the second encoder is used,
- wherein the first encoder is always used to produce the first code and the second encoder is optionally used to produce the second code, and
- wherein the second code together with the first code provides a stronger encoding than the first code alone.
4 more elements
A coding mechanism implemented in hardware, comprising:
- a first decoder to produce a first result for a data and a first code, the first code including a base number of bits;
- a second decoder to produce a second result for the data and at least a second code, the second code including a supplementary number of bits;
- storage for a mode register;
- and
- a switch responsive to the mode register to control whether or not the second decoder is used,
- wherein the first decoder is always used to produce the first result and the second decoder is optionally used to produce the second result, and
- wherein the second result together with the first result provides a stronger decoding than the first result alone.
4 more elements
A method, comprising:
- receiving data for a memory transaction;
- determining a number of bits available for error management during the memory transaction, wherein the number of bits available for error management include a base number of bits and a supplementary number of bits;
- performing a first error management coding for the data based on the base number of bits;
- and
- performing a second error management coding for the data based on the supplementary number of bits.
2 more elements
Dependencies are inferred from the claim text.