Methods for operating multicore processors

Abstract

The disclosure relates to at least two processor cores of a multicore processor for dual-lane computing of a security-critical application. The two processor cores are used to full capacity in different working cycles for computing operations of different applications, rather than computing operations being redundantly carried out by both processor cores in each computing cycle. This advantageously avoids duplication of the computational capacity required. For the processor cores to monitor each other, the computing operations are alternatingly carried out by the two processor cores. Any errors may be avoided by the error detection mechanisms described. Although the quality of the error detection is somewhat lower than the “dual-lane operation” known from the prior art with parallel, redundant multi-lane calculations, the quality of the error detection may satisfy the requirement of lower computational outlay, (e.g., when an economic implementation of the control system is required). The disclosure therefore combines the requirements of a sufficiently secure error detection with an economic distribution of the computational capacity.

Dependencies are inferred from the claim text.