Performance optimization of hardware accelerators

A computer program product being tangibly stored on a non-transitory machine-readable medium and comprising machine-executable instructions, the instructions, when executed on a device, causing the device to:

• receive, from a hardware accelerator device associated with the host, status information of a first acceleration task being executed by the hardware accelerator device, wherein the status information of the first acceleration task is received before termination of the first acceleration task, the status information indicating at least one of a cache miss/hit rate of the first acceleration task or a latency of data fetch by the first acceleration task;
• prepare for a second acceleration task to be executed by the hardware accelerator device based on the status information before termination of the first acceleration task;
• and
• provide the preparation for execution of the second acceleration task to the hardware accelerator device for executing the second acceleration task.

A system comprising:

• a host;
• and
• a hardware accelerator device communicatively coupled to the host;
• wherein the hardware accelerator device comprises an integrated circuit configured, using a Hardware Description Language (HDL), to perform one or more functions;
• wherein the integrated circuit is configured to:
• execute a first acceleration task assigned by the host to be executed on the hardware accelerator device;
• detect status information of the first acceleration task before termination of the first acceleration task;
• and
• provide the detected status information to the host before termination of the first acceleration task;
• wherein the host comprises one or more processor cores configured to:
• receive from the hardware accelerator device, the status information of the first acceleration task, wherein the status information of the first acceleration task is received before termination of the first acceleration task, the status information indicating at least one of a cache miss/hit rate of the first acceleration task or a latency of data fetch by the first acceleration task;
• prepare for a second acceleration task during execution of the first acceleration task and before termination of the first acceleration task, the second acceleration task to be executed by the hardware accelerator device;
• and
• provide the preparation for the second acceleration task to the hardware accelerator device for executing the second acceleration task;
• wherein the integrated circuit of the hardware accelerator device is configured to execute the second acceleration task based on the preparation for the second acceleration task.