Memory device, and data processing method based on multi-layer rram crossbar array

A memory device comprising:

• a control bus;
• and
• a memory unit connected to the control bus, the memory unit comprising a control circuit and a computation circuit,
• wherein the computation circuit comprises a first resistive random access memory (RRAM) crossbar having multiple rows and multiple columns of memory cells and multiple word lines connected to respective rows of memory cells, and a plurality of comparator circuits each connected to a corresponding column of the first RRAM crossbar array, wherein the comparator circuits are set to have incremental thresholds;
• wherein the control circuit is connected to the control bus and configured to:
• receive a computation instruction;
• parse the computation instruction into an instruction to perform a vector multiplication of vector A and vector B;
• setting the memory cells in the first RRAM crossbar array in the computation circuit such that states of memory cells of each column of the first RRAM crossbar array correspond to elements of vector B;
• and
• setting the word lines of the first RRAM crossbar array according to elements of vector A,
• wherein the outputs of the comparator circuits are voltage signals corresponding to a first binary number in which a number of bits with a value 1 indicates a numerical result of multiplication of vector A and vector B.

A computing device, comprising:

• a processor configured to send a computation instruction;
• a memory device connected to the processor, wherein the memory device comprising a control bus and a memory unit connected to the control bus, the memory unit comprising a control circuit and a computation circuit;
• wherein the computation circuit comprises a first resistive random access memory (RRAM) crossbar having multiple rows and multiple columns of memory cells and multiple word lines connected to respective rows of memory cells, and a plurality of comparator circuits each connected to a corresponding column of the first RRAM crossbar array, wherein the comparator circuits are set to have incremental thresholds;
• wherein the control circuit is connected to the control bus and configured to:
• receive the computation instruction;
• parse the computation instruction into an instruction to perform a vector multiplication of vector A and vector B;
• setting the memory cells in the first RRAM crossbar array in the computation circuit such that states of memory cells of each column of the first RRAM crossbar array correspond to elements of vector B;
• setting the word lines of the first RRAM crossbar array according to elements of vector A;
• wherein the outputs of the comparator circuits are voltage signals corresponding to a first binary number in which a number of bits with a value 1 indicates a numerical result of multiplication of vector A and vector B.