System and method for reducing non-linearity in mixed signal processing using complex polynomial vector processor

A system for processing high-speed data stream to reduce non-linearity in a mixed signal processing design, wherein the system comprising:

• a complex polynomial vector processor (102) that comprises
• (i) a co-efficient feeder unit (106) that calculates co-efficient for a polynomial, wherein the co-efficient feeder unit (106) comprises
• (a) an instruction memory (218) that comprises a Very Long Instruction Word (VLIW) to configure a gain for the high-speed data stream, wherein the high-speed data stream comprises a complex polynomial;
• (b) an instruction decoder (220) that is connected with the instruction memory (218) to read a next instruction from the instruction memory (218) to provide a co-efficient for the complex polynomial;
• and
• (c) a clock gater unit (222) that controls the co-efficient feeder (106) to reduce a size of the instruction memory (218);
• and
• (ii) a data processing unit (104) that processes the high-speed data stream in the mixed signal processing design for (i) increasing a processing speed and (ii) reducing non-linearity, wherein the data processing unit (104) comprises,
• (a) a normalized cordic transform unit (202) that converts the high-speed data stream into a polar-like (PL) format to obtain PL format data, wherein the complex polynomial of the high-speed data stream are amplified before converting into PL format data, wherein the PL format data comprises (i) a normalized theta that reduces complexity of accumulators of the complex polynomial vector processor (102) and (ii) real data that is applied to a shift register and a sigma delta Digital to Analog Converter (DAC) of the complex polynomial vector processor (102) to track an envelope of a power amplifier of the complex polynomial vector processor (102);
• (b) a polynomial power calculation unit (204) that calculates required polynomial power for the high-speed data stream based on the co-efficient of the complex polynomial and the PL format data, wherein the co-efficient of the complex polynomial is obtained from a co-efficient update unit (216), wherein the co-efficient update unit (216) is connected with the co-efficient feeder unit (106) for receiving the co-efficient of the complex polynomial;
• (c) a multiplier accumulator (MAC) unit (206) that processes the calculated polynomial power to generate processed high-speed data, wherein the MAC unit (206) receives the calculated polynomial powers from the polynomial power calculation unit (204) through one or more programmable gains (210A-N), wherein the one or more programmable gains (210A-N) coarse scales the co-efficient of the complex polynomial;
• (d) a delay unit (208) that combines the processed high-speed data with time separated input to generate output data, wherein the co-efficient update unit (216) applies a fine scaling to the co-efficient of the polynomial in at least one of the polynomial power calculation unit (204), the MAC unit (206) or the delay unit (208), wherein the polynomial co-efficient provided to at least one of the polynomial power calculation unit (204), the MAC unit (206) or a delay unit (208) to remove a maintenance of a shadow memory unit of the complex polynomial vector processor (102);
• and
• (e) an inverse cordic transform unit (214) that is connected to the MAC unit (206) and the delay unit (208) to convert the output data generated by the delay unit (208) to a Cartesian format from the PL format to obtain the Cartesian format output data with reduced non-linearity.