Instructions for dual destination type conversion, mixed precision accumulation, and mixed precision atomic memory operations
AssigneeIntel Corporation
InventorsWilliam M. Brown, Karthik Raman
Life of this patent
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AssigneeIntel Corporation
InventorsWilliam M. Brown, Karthik Raman
Estimating the term…
Disclosed embodiments relate to instructions for dual-destination type conversion, accumulation, and atomic memory operations. In one example, a system includes a memory, a processor including: a fetch circuit to fetch the instruction from a code storage, the instruction including an opcode, a first destination identifier, and a source identifier to specify a source vector register, the source vector register including a plurality of single precision floating point data elements, a decode circuit to decode the fetched instruction, and an execution circuit to execute the decoded instruction to: convert the elements of the source vector register into double precision floating point values, store a first half of the double precision floating point values to a first location identified by the first destination identifier, and store a second half of the double precision floating point values to a second location.
A system used to execute an instruction, the system comprising:
A method of executing an instruction, the method comprising:
An apparatus for executing an instruction, the apparatus comprising:
Dependencies are inferred from the claim text.