Method and system to provide user-level multithreading

A processor comprising:

• a first plurality of cores having first performance and power characteristics;
• a second plurality of cores having second performance and power characteristics, different from the first performance and power characteristics;
• each of the first and second plurality of cores to support a 64-bit instruction set architecture (ISA) and a 32-bit ISA,
• each core of the first and second plurality of cores comprising 64-bit architectural registers to be used when executing both 64-bit ISA instructions of a first thread and 32-bit ISA instructions of a second thread, each core to map 32-bit architectural registers of the 32-bit ISA to one or more of the 64-bit architectural registers during execution of the 32-bit ISA instructions of the second thread;
• a first plurality of physical 128-bit registers of a first core to store packed data elements for single instruction multiple data (SIMD) operations of the first thread;
• a second plurality of physical 128-bit registers of a second core to store packed data elements for single instruction multiple data (SIMD) operations of the second thread;
• a first plurality of control registers of the first core to store one or more variables related to a current execution state of the first thread;
• and
• a second plurality of control registers of the second core to store one or more variables related to a current execution state of the second thread.