Resistance switching memory-based accelerator

A resistance switching memory-based accelerator configured to be connected to a host including a central processing unit (CPU) and a system memory, the resistance switching memory-based accelerator comprising:

• a resistance switching memory module that stores kernels offloaded from the host, and includes a plurality of resistance switching memory cells divided into a plurality of partitions including a first partition and a second partition, and a plurality of row data buffers including a first row data buffer and a second row data buffer;
• an accelerator core including a plurality of processing elements, each kernel being executed by a corresponding target processing element among the plurality of processing elements;
• a memory controller unit (MCU) that manages memory requests generated in accordance with execution of each kernel by the target processing element;
• a memory controller that is connected to the resistance switching memory module, and processes a first operation in accordance with a first memory request and a second operation in accordance with a second memory request in parallel, the first operation of bringing first data from the first partition to the first row data buffer, and the second operation of moving second data from the second row data buffer to the target processing element corresponding to the second memory request;
• and
• a network that integrates the resistance switching memory module, the accelerator core, and the memory controller.

A resistance switching memory-based accelerator configured to be connected to a host including a central processing unit (CPU) and a system memory, the resistance switching memory-based accelerator comprising:

• a resistance switching memory module that stores a kernel offloaded from the host and includes a memory cell array including a plurality of resistance switching memory cells;
• an accelerator core including a plurality of processing elements, the kernel being executed by a target processing element among the plurality of processing elements;
• a memory controller unit (MCU) that manages memory requests generated in accordance with execution of the kernel by the target processing element;
• a memory controller that is connected to the resistance switching memory module, allows data according to the memory request to move between the resistance switching memory module and the target processing element in accordance with the memory request transferred from the MCU, and programs predetermined data for addresses of the memory cell array to be overwritten by the execution of the kernel.
• a network that integrates the accelerator core, the plurality of processing elements, and the memory controller.