System and method for processing non-contiguous submission and completion queues
AssigneeWestern Digital Technologies, Inc.
InventorShay Benisty
Life of this patent
Estimating the term…
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AssigneeWestern Digital Technologies, Inc.
InventorShay Benisty
Estimating the term…
Systems and methods for processing non-contiguous submission and completion queues are disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The submission and completion queues may be contiguous or non-contiguous in host device memory. Non-contiguous queues may be defined by a link to a list on the host device that lists the non-contiguous sections in memory. In practice, the memory device stores the list in one type of memory (such as DRAM) and the link in a different type of memory (such as always on memory or non-volatile memory). In this way, the link may be accessed in various modes (such as low power mode) in order to recreate the list in DRAM.
A method comprising:
A memory device comprising:
A non-volatile memory device comprising:
Dependencies are inferred from the claim text.