Flash-based accelerator and computing device including the same

A flash-based accelerator configured to be connected to a host including a central processing unit (CPU) and a system memory, the flash-based accelerator comprising:

• a flash backbone including a flash memory and a flash controller;
• a plurality of processors that execute a plurality of kernels offloaded from the host;
• a memory system including a first memory that is used to map a data section of each kernel to the flash memory, and a second memory that stores mapping information for translating a word- or byte-based address mapped to a region of the first memory pointed by the data section to a physical address in the flash memory;
• a supervisor processor that, when read data are read from the flash memory in accordance with execution of each kernel, translates the word- or byte-based address to the physical address of the flash memory based on the mapping information, and transfers a memory request to the flash controller to allow the read data to move from the flash memory to the region of the first memory.
• a network that integrates the flash backbone, the memory system, the plurality of processors, and the supervisor processor.