Speculatively performing memory move requests with respect to a barrier

A processing unit for a data processing system implementing a weak memory model, wherein the data processing system includes an interconnect fabric, the processing unit comprising:

• a processor core having a store-through upper level cache and a store-in lower level cache, wherein the lower level cache includes a plurality of state machines including a first state machine and a second state machine, and wherein the lower level cache is configured to perform:
• receiving, from the processor core, a plurality of copy-type requests and a plurality of paste-type requests that together indicate a memory move to be performed;
• receiving, from the processor core, a barrier request that requests enforcement of ordering of memory access requests prior to the barrier request with respect to memory access requests after the barrier request, wherein the barrier request precedes a copy-type request and a paste-type request of the memory move in program order;
• prior to completion of processing of the barrier request by the lower level cache, speculatively reading a data granule identified by a source real address of the copy-type request into a non-architected buffer;
• and
• after processing of the barrier request is complete, writing the data granule from the non-architected buffer to a storage location identified by a destination real address of the paste-type request.

A design structure tangibly embodied in a computer-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• a processing unit for a data processing system implementing a weak memory model, wherein the data processing system includes an interconnect fabric, the processing unit comprising:
• a processor core having a store-through upper level cache and a store-in lower level cache, wherein the lower level cache includes a plurality of state machines including a first state machine and a second state machine, and wherein the lower level cache is configured to perform:
• receiving, from the processor core, a plurality of copy-type requests and a plurality of paste-type requests that together indicate a memory move to be performed;
• receiving, from the processor core, a barrier request that requests enforcement of ordering of memory access requests prior to the barrier request with respect to memory access requests after the barrier request, wherein the barrier request precedes a copy-type request and a paste-type request of the memory move in program order;
• prior to completion of processing of the barrier request by the lower level cache, speculatively reading a data granule identified by a source real address of the copy-type request into a non-architected buffer;
• and
• after processing of the barrier request is complete, writing the data granule from the non-architected buffer to a storage location identified by a destination real address of the paste-type request.