Self-adaptive startup compensation device

A self-adaptive startup compensation device, comprising:

• a reference voltage generating circuit, including:
• first to fifth transistors, an input terminal of the first transistor is connected to a voltage source, an output terminal of the first transistor is connected to input terminals of the second and third transistors, an output terminal of the second transistor is connected to a control terminal of the second transistor, an input terminal of the fourth transistor and a control terminal of the fifth transistor, an output terminal of the third transistor is connected to a control terminal of the third transistor and an input terminal of the fifth transistor, the output terminal of the third transistor is grounded through a first capacitor, and output terminals of the fourth and fifth transistors are grounded;
• first and second current mirrors, input terminals of the first current mirror are connected to the output terminal of the first transistor, first and second output terminals of the first current mirror are connected to input terminals of the second current mirror respectively, the second output terminal of the first current mirror is connected to control terminals of the first and fourth transistors;
• and
• a DC-to-DC converter, including:
• first and second transconductance amplifiers, a non-inverting input terminal of the first transconductance amplifier and an inverting input terminal of the second operational transconductance amplifier are connected to one terminal of the first capacitor that is connected to the third transistor, an inverting input terminal of the first transconductance amplifier and a non-inverting input terminal of the second operational transconductance amplifier are connected to the second output terminal of the first current mirror;
• an error amplifier having a bias input terminal connected to an output terminal of the first transconductance amplifier, a first non-inverting input terminal connected to the one terminal of the first capacitor in a decreasing frequency mode, and a second non-inverting input terminal connected to the second output terminal of the first current mirror in a constant frequency mode;
• a clock circuit having an input terminal connected to an output terminal of the second operational transconductance amplifier;
• a PWM controller and a RAMP generator, each of which has one input terminal connected to an output terminal of the clock circuit;
• a comparator having an inverting input terminal and a non-inverting input terminal which are connected to output terminals of the error amplifier and the RAMP generator respectively, and an output terminal connected to another input terminal of the PWM controller;
• and
• a switch circuit connected to an inverting input terminal of the error amplifier and an output terminal of the PWM controller.