US 2018/0321314 A1Published application

On-chip sequence profiler

AssigneeInternational Business Machines Corporation

InventorsBenedikt Geukes, Manfred Walz, Matteo Michel

Life of this patent

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Abstract

A method, circuit, and design structure for an on-chip sequence profiler involves a programmable matrix and FSM in a logic circuit, a first latch receiving a scan path bit sequence and a first clock signal and generating a first output to control a select input of a first multiplexer, a first multiplexer selecting among functional path bit sequences and outputting a bit sequence to a second latch, a second latch receiving the bit sequence from the first multiplexer and a second clock signal via a second multiplexer and outputting a bit sequence to a logic circuit, a logic circuit receiving the bit sequence from the second latch and outputting a clock control signal to the clock and a second selector control signal to the second multiplexer, and a second multiplexer receiving a second clock signal from the clock and outputting the second clock signal to the second latch.

Claims19

Dependent claims

A method for profiling on-chip application sequences comprising:

generating, for a profiling event to track a first bit sequence as it is applied to the internal latches of a chip and to determine whether the first bit sequence was executed successfully, a matrix for a logic circuit, the matrix having a first dimension corresponding to a sequence of time periods in the profiling event and a second dimension corresponding to a set of profilers, wherein a programmable element of the matrix stores a control signal applied to a first profiler during a first time period of the sequence of time periods;
storing, in a first latch of the first profiler, a first bit of a scan sequence;
selecting, by a first multiplexer of the first profiler based on the first bit, a first bit sequence of a set of two or more bit sequences;
determining, by a second multiplexer of the first profiler based on the control signal, whether to capture the first bit sequence;
latching, by a second latch of the first profiler in response to determining to capture the first bit sequence, a second bit of the first bit sequence during the first time period;
determining, by the logic circuit, whether the latched second bit has an expected value, the expected value indicated by the control signal and the first time period;
and
disabling, in response to determining that the second bit has the expected value, the second latch.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/585,203Filed 3 May 2017
Published: 8 Nov 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G01R 31/318525
Test of Sequential circuits: test of flip-flops or latches
G01R 31/318541
Using scanning techniques, e.g. LSSD, Boundary Scan, JTAG: scan latches or cell details
G01R 31/318583
Using scanning techniques, e.g. LSSD, Boundary Scan, JTAG: design for test
G01R
Measuring electric variables

Family

US 10,156,610 B2Related patent
US 2018/0321314 A1This patent

From the US filing history. Foreign family members aren’t listed.

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