Methods of tunnel oxide layer formation in 3d nand memory structures and associated devices
AssigneeIntel Corporation
InventorsDarwin Fan, Sateesh Koka, Gordon Haller, John Hopkins, Shyam Surthi, Anish Khandekar
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Abstract
3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating gate material and control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material deposited on the floating gate material opposite the control gate material.
Claims25
1-24. (canceled)
A 3D NAND memory structure comprising:
- a control gate and a floating gate disposed between a first insulating layer and a second insulating layer;
- an interpoly dielectric (IPD) layer disposed between the control gate and the floating gate such that the IPD layer electrically isolates the control gate from the floating gate;
- and
- a tunnel dielectric layer coupled to the floating gate opposite the control gate, wherein the floating gate is substantially free of curves at an interface with the tunnel dielectric layer.
A method of forming a tunnel dielectric layer in a 3D NAND memory structure comprising:
- creating a layer of material on an exposed surface of a floating gate in a cell stack substrate, wherein said material either operates as the tunnel dielectric layer without further treatment, or operates as the tunnel dielectric layer after further treatment of the material.
Dependencies are inferred from the claim text.