Vertical stack memory device

A vertical stack memory device comprising:

• a doped semiconductor substrate having a common source configured to receive a source power;
• a stack gate structure having gate electrodes and insulation interlayer patterns that are alternately and vertically stacked on the substrate in a first direction;
• a channel structure penetrating through the stack gate structure in the first direction and connected to the substrate through a low band gap via-pattern comprising low band gap materials;
• and
• a charge storage structure interposed between the stack gate structure and the channel structure and selectively storing charge as a memory data, the gate electrode and the charge storage structure and the channel structure corresponding to the gate electrode being configured into a memory cell of the vertical stack memory device.

A stacked memory device, comprising:

• a semiconductor substrate;
• a plurality of memory cells stacked vertically on the semiconductor substrate, wherein the semiconductor substrate includes a common source for the plurality of memory cells, and wherein the semiconductor substrate includes a low band gap layer comprising one or more low band gap materials;
• a stack gate structure for the plurality of memory cells;
• a channel structure for the plurality of memory cells;
• and
• a charge storage structure configured to store charge and to provide the stored charge to the plurality of memory cells.