Resistive interpolation for an amplifier array

A circuit for analog-to-digital conversion, comprising:

• an input terminal to receive an input value;
• at least one folding interpolated amplifier array, including
• a folding amplifier stage with M amplifiers (M≥4), each coupled to the input terminal to receive the input value, the M amplifiers configured with a folding factor of N (N≥2) to provide M/N amplifier stage outputs;
• a resistor interpolator coupled to receive the M/N amplifier stage outputs, and configured to provide an interpolation order N (N≥2), and including
• an input row and at least a second row, each row comprising multiple interpolation resistors connected in series at nodes,
• the input row including M/N driven nodes connected to a respective amplifier, and (N−1) interpolation nodes intermediate each of adjacent driven nodes, and
• the input row connected in parallel to the second row, with at least some of the interpolation nodes of the first row connected to corresponding interpolation nodes of the second row;
• the resistor interpolator including at least one multi-row interpolation cell, comprising:
• in the input row, a driven node connected to first and second interpolation resistors connected between the driven node and respective adjacent first and second interpolation nodes;
• in the second row, third and fourth interpolation resistors connected between respective third and fourth interpolation nodes and an intermediate fifth interpolation node;
• the first and second interpolation nodes of the input row connected respectively to the third and fourth interpolation nodes of the second row.