Data processing circuit of digital television and method thereof

A data processing circuit, applied for a multiplexing process and a bit de-interleaving process of a digital television, a de-mapping circuit of the digital television generating a plurality of orthogonal frequency division multiplexing (OFDM) symbols, the data processing circuit comprising:

• a buffer, coupled to the de-mapping circuit, storing a target OFDM symbol, which is one among the plurality of OFDM symbols;
• a write address generating circuit, generating a write address for each data bit of the target OFDM symbol according to a sequence number of the target OFDM symbol;
• a read address generating circuit, generating a read address for each data bit of the target OFDM symbol according to a counter value;
• and
• a memory controller, writing each data bit of the target OFDM symbol into a memory according to the write addresses, and reading each data bit of the OFDM symbol from the memory according to the read addresses;
• wherein, each data bit of the target OFDM symbol is subjected to one write operation and one read operation, and the target OFDM symbol read from the memory has completely undergone the multiplexing process and the bit de-interleaving process.