Mitigating interaction between adaptive equalization and timing recovery

A device for signal processing, said device comprising:

• an equalizer configured to generate an equalized signal responsive to a digital input signal, wherein said equalizer comprises an equalization filter;
• and
• compensation logic coupled to said equalizer and configured to:
• detect a correction in clock delay associated with said digital input signal, wherein said correction is introduced by said equalizer;
• and
• adjust said equalization filter based on said correction in clock delay to compensate said correction.

A receiver comprising:

• an analog-to-digital converter (ADC) configured to generate a digital input signal responsive to a received signal;
• a timing recovery loop coupled to said ADC and comprising:
• an equalizer configured to generate an equalized signal responsive to said digital input signal and through an adaptive equalization process, wherein said equalizer comprises an equalization filter, and wherein said adaptive equalization process results in correction of clock delay associated with said digital input signal;
• compensation logic coupled to said equalizer and configured to compensate said correction by updating said equalized filter;
• and
• a phase detector coupled to said equalizer.