Enhancing robustness of soi substrate containing a buried n+ silicon layer for cmos processing
AssigneeInternational Business Machines Corporation
InventorsStephen W. Bedell, Stephan A. Cohen, Joel P. de Souza, Karen A. Nummy, Daniel J. Poindexter, Devendra K. Sadana
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Abstract
A silicon buffer layer selected from undoped silicon, p-doped silicon or a multilayered stack of, in any order, undoped silicon and p-doped silicon is provided between an n+ silicon layer and an oxide layer of an SOI substrate. The presence of the silicon buffer layer reduces electron injection into the oxide layer during device processing which requires an electric field.
Claims16
A semiconductor-on-insulator (SOI) substrate comprising from bottom to top,
- a silicon handle substrate;
- an n+ silicon layer;
- a silicon buffer layer consisting of undoped silicon;
- an oxide layer;
- and
- a p− silicon layer.
A semiconductor-on-insulator (SOI) substrate comprising from bottom to top,
- a silicon handle substrate;
- an n+ silicon layer;
- a silicon buffer layer consisting of p-doped silicon;
- an oxide layer;
- and
- a p− silicon layer.
A semiconductor-on-insulator (SOI) substrate comprising from bottom to top,
- a silicon handle substrate;
- an n+ silicon layer;
- a silicon buffer layer consisting of a multilayered stack of, in any order, undoped silicon and p-doped silicon;
- an oxide layer;
- and
- a p− silicon layer.
Dependencies are inferred from the claim text.