Apparatus and methods including source gates

A memory array, comprising:

• multiple strings of charge storage devices, each string comprising multiple charge storage devices associated with a respective pillar comprising semiconductor material, wherein the multiple strings of charge storage devices are arranged in rows and columns, each of the multiple strings coupled to a common source through both a source gate device and a source select gate device;
• wherein each source gate device includes a gate, and is configured to partially control conduction between the pillar of the respective string and the common source,
• wherein each source select gate device includes a gate and is also configured to partially control conduction between the pillar of the respective string and the common source,
• wherein the gates of the source gate devices associated with each of the multiple strings of charge storage devices are coupled together to be controlled in common;
• and
• wherein the gates of source select gate devices associated with a first group of strings of the multiple strings of charge storage devices are coupled together to be controlled in common, wherein the first group of strings is less than all of the multiple strings of charge storage devices.

A memory device, comprising:

• multiple strings of charge storage devices in a block of memory, each string comprising multiple charge storage devices associated with a respective pillar comprising semiconductor material, wherein the multiple strings of charge storage devices are arranged in rows and columns in the block of memory;
• multiple drain select gate devices, each drain select gate device at least partially surrounding a respective pillar of one of the multiple strings of charge storage devices,
• wherein the drain select gate device is between the string of charge storage devices associated with the pillar and a respective data line, and
• wherein the gates of drain select gate devices associated with a first group of strings are coupled to one another to be controlled in common;
• multiple source gate devices, each source gate at least partially surrounding a respective pillar of one of the multiple strings, each source gate device coupled to a source and configured to partially control conduction between the pillar and the source,
• wherein each source gate device includes a gate,
• wherein the gate of each source gate device is coupled to the gates of multiple additional source gate devices associated with a second group of strings of charge storage devices, and
• wherein the second group of strings includes a source gate device of a string in the same row, and further includes the gate of a source gate device in another row, to be controlled in common;
• and
• multiple source select gate devices, each source select gate device at least partially surrounding a respective pillar of one of the multiple strings,
• wherein each source select gate device is between the plurality of string of charge storage devices associated with the pillar and the source gate device, and is configured to partially control conduction between the pillar and the source, and
• wherein the source select gate devices associated with the first group of strings are coupled to one another to be controlled in common.

A method for operating a memory array, wherein the memory array comprises:

• multiple strings of charge storage devices, each string comprising multiple charge storage devices associated with a respective pillar comprising semiconductor material, wherein the multiple strings of charge storage devices are arranged in rows and columns, each of the multiple strings coupled to a common source through both of a source gate device and a source select gate device;
• wherein each source gate device includes a gate, and is configured to partially control conduction between the pillar of the respective string and the common source,
• wherein each source select gate device includes a gate and is configured to partially control conduction between the pillar of the respective string and the common source,
• wherein the gates of the source gate devices associated with each of the multiple strings of charge storage devices are coupled together to be controlled in common;
• wherein the gates of source select gate devices associated with a first group of strings of the multiple strings of charge storage devices are coupled together to be controlled in common, wherein the first group of strings is less than all of the multiple strings of charge storage devices;
• and
• wherein the multiple charge storage devices each includes a respective gate, and wherein the gates of individual respective charge storage devices, one from each string of a second group of strings of the multiple strings of charge storage devices, are coupled to a respective access line to be controlled in common;
• the method comprising:
• biasing the common source to a first voltage;
• controlling a first source select device to an “on” state, the first source select gate device associated with a selected string of charge storage devices, while controlling multiple source select gate devices associated with unselected strings of charge storage devices to an “off” state;
• controlling the source gate devices associated with both the selected string of charge storage devices and the unselected strings of charge storage devices to an “on” state;
• biasing, with the read voltage, a selected access line coupled to a selected charge storage device in the selected string of charge storage devices;
• and
• biasing multiple unselected access lines with a voltage greater than the read voltage, the unselected access lines coupled to multiple charge storage devices other than the selected charge storage device.