Memory device, memory system, and memory control method

A memory device, comprising:

• a plurality of memory cells in a matrix arrangement, the plurality of the memory cells each including a current path that includes a selection element and a variable resistance element coupled in series to each other;
• a plurality of row wirings extending in a row direction, the plurality of the row wirings each being coupled to one end of the current path;
• a plurality of column wirings extending in a column direction, the plurality of the column wirings each being coupled to another end of the current path;
• a first decoder circuit coupled to each of the row wirings of even-numbered rows;
• a second decoder circuit coupled to each of the row wirings of odd-numbered rows;
• a third decoder circuit coupled to each of the column wirings of even-numbered columns;
• and
• a fourth decoder circuit coupled to each of the column wirings of odd-numbered columns,
• the first decoder circuit, the second decoder circuit, the third decoder circuit, and the fourth decoder circuit being constituted by independent circuits from one another.

A memory control method in a memory device including

• a plurality of memory cells in a matrix arrangement, the plurality of the memory cells each including a current path that includes a selection element and a variable resistance element coupled in series to each other,
• a plurality of row wirings extending in a row direction, the plurality of the row wirings each being coupled to one end of the current path,
• a plurality of column wirings extending in a column direction, the plurality of the column wirings each being coupled to another end of the current path,
• a first decoder circuit coupled to each of the row wirings of even-numbered rows,
• a second decoder circuit coupled to each of the row wirings of odd-numbered rows,
• a third decoder circuit coupled to each of the column wirings of even-numbered columns, and
• a fourth decoder circuit coupled to each of the column wirings of odd-numbered columns,
• the memory control method comprising
• controlling the first decoder circuit, the second decoder circuit, the third decoder circuit, and the fourth decoder circuit independently from one another.