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US 2018/0121120 A1Published application
Scaling out architecture for dram-based processing unit (dpu)
AssigneeSamsung Electronics Co., Ltd.
InventorsDimin Niu, Shuangchen Li, Bob Brennan, Krishna T. Malladi, Hongzhong Zheng
Life of this patent
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Abstract
A processor includes a plurality of memory units, each of the memory units including a plurality of memory cells, wherein each of the memory units is configurable to operate as memory, as a computation unit, or as a hybrid memory-computation unit.
Claims20
A processor comprising:
- a plurality of memory units, each of the memory units comprising a plurality of memory cells,
- wherein each of the memory units is configurable to operate as memory, as a computation unit, or as a hybrid memory-computation unit.
A method of controlling work flow in a distributed computation system comprising a plurality of memory units, the method comprising:
- receiving work flow comprising a job to be performed by one or more of the memory units;
- performing by one of the memory units the job or a portion of the job according to the work flow;
- and
- forwarding by the one of the memory units a remainder of the work flow to another one of the memory units after completion of the job or the portion of the job.
1 more element
A method of controlling work flow in a distributed computation system comprising a plurality of memory units, the method comprising:
- receiving a first request from a host to perform a first job by one of the memory units;
- performing the first job by the one of the memory units;
- providing a result of the first job to the host from the one of the memory units;
- and
- receiving a second request from the host to perform a second job by another one of the memory units.
2 more elements
Dependencies are inferred from the claim text.