Technologies for sled architecture
AssigneeIntel Corporation
InventorsMatthew J. Adiletta, Aaron Gorius, Myles Wilde, Michael T. Crocker
Life of this patent
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Abstract
A sled for operation in a corresponding rack of a data center includes a chassis-less circuit board substrate having one or more physical resources coupled to a top side of the chassis-less circuit board and one or more memory devices coupled to a bottom side of the chassis-less circuit board. The sled does not include a housing or chassis and is opened to the local environment. In the illustrative embodiments, the sled may be embodied as a compute sled, an accelerator sled, or a storage sled.
Claims25
A sled for operation in a rack of a data center, the sled comprising:
- a chassis-less circuit board substrate having a top side and a bottom side opposite the top side;
- one or more physical resources coupled to the top side of the chassis-less circuit board substrate;
- and
- one or more memory devices coupled to the bottom side of the chassis-less circuit board substrate, wherein each of the one or more memory devices is electrically coupled to at least one of the one or more physical resources.
A compute sled for operation in a rack of a data center, the compute sled comprising:
- a chassis-less circuit board substrate having a top side and a bottom side opposite the top side;
- a plurality of processors coupled to the top side of the chassis-less circuit board substrate;
- and
- a plurality of memory devices coupled to the bottom side of the chassis-less circuit board substrate, wherein each of the plurality of memory devices is electrically coupled to at least one of the plurality of processors.
An accelerator sled for operation in a rack of a data center, the accelerator sled comprising
- a chassis-less circuit board substrate having a top side and a bottom side opposite the top side;
- a plurality of accelerator circuits coupled to the top side of the chassis-less circuit board substrate;
- and
- a plurality of memory devices coupled to the bottom side of the chassis-less circuit board substrate, wherein each of the plurality of memory devices is electrically coupled to at least one of the plurality of accelerator circuits.
Dependencies are inferred from the claim text.