Ethernet auto-negotiation with parallel detect for 10g dac or other non-auto-negotiated modes

An Ethernet apparatus comprising:

• a receiver, configured to receive Ethernet signals in accordance with at least one Institute of Electrical and Electronics Engineers (IEEE) 802.3 Ethernet specification supporting auto-negotiation (AN) and Ethernet signals in accordance with at least one Ethernet specification that does not support AN.
• a transmitter, configured to transmit Ethernet signals in accordance with the at least one IEEE 802.3 Ethernet specification supporting AN and Ethernet signals in accordance with the at least one Ethernet specification that does not support AN;
• a first block of physical layer (PHY) circuitry configured to perform PHY processing of Ethernet signals in accordance with the at least one IEEE 802.3 Ethernet specification supporting AN;
• a second block of PHY circuitry configured to perform PHY processing of Ethernet signals in accordance with the at least one Ethernet specification that does not support AN;
• and
• an auto-negotiation module, comprising circuitry and logic configured to perform AN operations in accordance with the at least one IEEE 802.3 Ethernet specification supporting AN,
• wherein the Ethernet apparatus is further configured to,
• transmit AN base pages via the transmitter to advertise the Ethernet apparatus has the ability to support at least one IEEE 802.3 Ethernet specification supporting AN;
• detect, at the receiver using a first detection mode, for a valid signal transmitted from an Ethernet link peer that does not support auto-negotiation (AN);
• and
• detect, at the receiver using a second detection mode, for AN pages transmitted from an IEEE 802.3 Ethernet link peer using an IEEE 802.3 Ethernet link technology supporting AN.

A multi-mode Ethernet Network Interface Controller (NIC) comprising:

• a receiver, configured to receive 10 Gigabit per second (10G) Ethernet signals;
• a transmitter, configured to transmit 10G Ethernet signals;
• a first physical layer (PHY) circuit block, selectively coupled to the receiver and transmitter and configured to process Institute of Electrical and Electronics Engineers (IEEE) 802.3 10 GBASE-KR Ethernet signals;
• a second PHY circuit block, selectively coupled to the receiver and transmitters and configured to process 10G Direct Attachment Cable (DAC) Ethernet signals,
• wherein the multi-mode Ethernet NIC is further configured, when coupled to an Ethernet port to which an Ethernet link peer is communicatively coupled via a copper cable, to detect whether the Ethernet link peer is transmitting 10G DAC Ethernet signals or 10 GBASE-KR Ethernet signals.