Data handoff between randomized clock domain to fixed clock domain

Abstract

A time-interleaved analog-to-digital converter (ADC) having M ADCs can increase the sampling speed several times compared to the sampling speed of just one ADC. Some time-interleaved ADCs randomize the order of the M ADCs sampling the analog input signal to improve dynamic performance. Randomization causes the output data of the M ADCs to be valid at randomized time instants. When the output data is sampled using a rising edge of a fixed clock, the output data can be valid just before, valid right at, or only valid for a short period of time after, the rising edge. Therefore, the setup or hold time can be very short. To address this issue, information regarding the randomized selection of an ADC is used to control the sampling occurring in the fixed clock domain and avoid the short setup or hold time.

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