FPGA RAM Blocks Optimized for Use as Register Files

A field programmable gate array integrated circuit device comprising:

• a programmable array having logic modules and routing interconnects programmably coupleable to the logic modules;
• a random-access memory circuit including first, second, and third ports, at least two of the first second, and third ports comprising a plurality of address input terminals and a plurality of data output terminals;
• a plurality of address input nodes associated with the random-access memory circuit, each address input node programmably coupleable to the routing interconnects;
• a plurality of data output nodes associated with the random-access memory circuit, each data output node programmably coupleable to the routing interconnects;
• an address clocked logic element associated with each of the address input nodes, each address clocked logic element having a data input coupled to a different one of the address input nodes, a clock input, and a data output;
• and
• a plurality of address input multiplexers, each address input multiplexer having a first data input coupled to the output of a different one of the address clocked input address input nodes, a second data input coupled to a different one of the address input nodes, a data output coupled to a different one of the address input terminals, and a select input.