On-die termination circuit, a memory device including the on-die termination circuit, and a memory system including the memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsJI-WOON PARK, BYUNG-HO KIM
Life of this patent
Estimating the term…
Abstract
An on-die termination (ODT) circuit connected to an input buffer that receives a data signal, the ODT circuit includes at least one termination resistor connected to the input buffer and at least one switching device configured to control a connection between the termination resistor and the input buffer. The switching device is turned on or off according to information about the data signal.
Claims25
An on-die termination circuit connected to an input buffer that receives a data signal, the on-die termination circuit comprising:
- at least one termination resistor connected to the input buffer;
- and
- at least one switching device configured to control a connection between the termination resistor and the input buffer;
- wherein the switching device is turned on or off according to information about the data signal,
- wherein the information about the data signal includes at least one of pattern information of the data signal, frequency information of the data signal, and length information of a channel through which the data signal is transmitted.
11-12. (canceled)
A memory device, comprising:
- an input buffer configured to receive a data signal;
- an on-die termination (ODT) circuit connected to the input buffer;
- and
- an ODT controller configured to detect a pattern of the data signal and control turning on and turning off of the ODT circuit in response to the pattern of the data signal.
(canceled)
A memory system, comprising:
- a memory device including a first memory device and a second memory device, the first memory device including at least one first on-die termination (ODT) circuit, and the second memory device including at least one second ODT circuit;
- and
- a memory controller configured to provide the first memory device with a first data signal through a first channel, provide the second memory device with a second data signal through a second channel, and control turning on and turning off of the first and second ODT circuits according to patterns of the first and second data signals, respectively.
(canceled)
24-25. (canceled)
27-29. (canceled)
Dependencies are inferred from the claim text.