Biasing scheme for high voltage circuits using low voltage devices

An apparatus comprising:

• an integrated circuit including a first node to receive a supply voltage and a second node to receive ground potential;
• and
• a transmitter located in the integrated circuit, the transmitter including a buffer to transmit a signal, the buffer including:
• an output stage including a first pair of transistors coupled between the first node and an output node, and a second pair of transistors coupled between the output node and the second node;
• and
• a bias stage to provide a first bias voltage to a gate of a transistor in the second pair of transistors and a second bias voltage to a gate of a transistor in the first pair of transistors, wherein a value of each of the first and second bias voltages is greater than zero, and the value of the second bias voltage is based on a value of the supply voltage and the value of the first bias voltage.

An apparatus comprising:

• an integrated circuit including a first node to receive a first voltage and a second node to receive a second voltage;
• and
• a transmitter located in the integrated circuit, the transmitter including a circuit to transmit a signal, the circuit including:
• a first stage including a first pair of transistors of a first transistor type coupled between the first node and an output node, and a second pair of transistors of a second transistor type coupled between the output node and the second node;
• and
• a second stage to provide a first bias voltage to a gate of a transistor in the second pair of transistors and a second bias voltage to a gate of a first transistor in the first pair of transistors, wherein a value of each of the first and second bias voltages is greater than zero, and the value of the second bias voltage is based on the value of the first voltage and the value of the first bias voltage.