High-speed continuous-time comparator circuit

A comparator circuit, comprising:

• an input circuit coupled to receive first and second input signals and configured to provide first and second current signals to first and second input nodes, respectively, based on the first and second input signals;
• a first current mirror including a first load transistor coupled to the first input node and including a first output transistor configured to generate a first mirrored current based on the first current signal, the first current mirror including a first resistive circuit to set a constant associated with the first load transistor to a first time constant value;
• a first feedback transistor including a conduction node coupled to the first input node and a control node coupled to the second input node, a second time constant being associated with the first feedback transistor where the second time constant has a second time constant value that is less than the first time constant value;
• a second current mirror including a second load transistor coupled to the second input node and including a second output transistor configured to generate a second mirrored current based on the second current signal, the second current mirror including a second resistive circuit to set a time constant associated with the second load transistor to the first time constant value;
• a second feedback transistor including a conduction node coupled to the second input node and a control node coupled to the first input node, the second time constant being associated with the second feedback transistor;
• and
• output circuitry coupled to the first and second output transistors and configured to generate an output signal based on the first and second mirrored currents.

A method of comparing first and second input signals, the method comprising:

• providing a first current to a first input node based on the first input signal;
• providing a second current to a second input node based on the second input signal;
• controlling a voltage on the first input node through a negative-feedback mechanism based upon the first current;
• controlling a voltage on the second input node through the negative-feedback mechanism based upon the second current;
• controlling the voltage on the first input node through a positive-feedback mechanism based upon the voltage on the second input node;
• controlling the voltage on the second input node through the positive-feedback mechanism based on the voltage on the first input node;
• generating first and second mirrored current based on the first and second currents, respectively;
• and
• generating an output signal based on the first and second mirrored currents.