Comparator, circuit device, physical quantity sensor, electronic device, and vehicle
AssigneeSeiko Epson Corporation
InventorHideo HANEDA
Life of this patent
Estimating the term…
Abstract
A comparator includes a first voltage-time conversion circuit, a second voltage-time conversion circuit, and a determination circuit. A first delay unit includes a first falling edge delay circuit that delays a falling edge based on a first input signal, a first rising edge delay circuit that delays a rising edge based on a second input signal, and a first output circuit. A second delay unit includes a second falling edge delay circuit that delays a falling edge based on the second input signal, a second rising edge delay circuit that delays a rising edge based on the first input signal, and a second output circuit.
Claims20
A comparator comprising:
- a first voltage-time conversion circuit which includes a first delay circuit, the first delay circuit being configured to receive a first input signal and a second input signal;
- a second voltage-time conversion circuit which includes a second delay circuit, the second delay circuit being configured to receive the first input signal and the second input signal;
- and
- a determination circuit communicating with the first and second voltage-time conversion circuits, the determination circuit being configured to determine a magnitude relation of the first input signal and the second input signal based on an output signal of the first voltage-time conversion circuit and an output signal of the second voltage-time conversion circuit,
- wherein the first delay circuit includes a first delay unit, the first delay unit including:
- a first falling edge delay circuit configured to delay a falling edge of an input signal received by the first delay unit based on the first input signal;
- a first rising edge delay circuit configured to delay a rising edge of the input signal received by the first delay unit based on the second input signal;
- and
- a first output circuit configured to generate a first delayed output signal based on an output signal from the first falling edge delay circuit and an output signal from the first rising edge delay circuit, and
- wherein the second delay circuit includes a second delay unit, the second delay circuit including:
- a second falling edge delay circuit configured to delay a falling edge of an input signal received by the second delay unit based on the second input signal;
- a second rising edge delay circuit configured to delay a rising edge of the input signal received by the second delay unit based on the first input signal;
- and
- a second output circuit configured to generate a second delayed output signal based on an output signal from the second falling edge delay circuit and an output signal from the second rising edge delay circuit.
Dependencies are inferred from the claim text.