Semiconductor device

A semiconductor device comprising:

• a first transistor, a second transistor, a third transistor, a fourth transistor, a latch circuit, and a memory circuit,
• wherein:
• each of the first transistor and the second transistor is an n-channel transistor,
• each of the third transistor and the fourth transistor is a p-channel transistor,
• one of a source and a drain of the first transistor is supplied with a low power supply voltage,
• the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
• the other of the source and the drain of the second transistor is electrically connected to the latch circuit and one of a source and a drain of the third transistor,
• the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
• the other of the source and the drain of the fourth transistor is supplied with a high power supply voltage,
• a gate of the first transistor is electrically connected to a gate of the fourth transistor,
• a gate of the second transistor is electrically connected to a gate of the third transistor, and
• the memory circuit is configured to store data stored in the latch circuit, while supply of a power supply voltage is stopped.

A semiconductor device comprising:

• a first terminal, a second terminal, a third terminal, a fourth terminal, a latch circuit, and a memory circuit,
• wherein:
• the fourth terminal outputs “false” when “false” is input to the first terminal, the second terminal, and the third terminal,
• the fourth terminal outputs “true” when “true” is input to the first terminal, the second terminal, and the third terminal,
• the fourth terminal outputs a truth value that is the same as a previous output, when “true” is input to at least one of the first terminal, the second terminal, and the third terminal and “false” is input to at least another one of the first terminal, the second terminal, and the third terminal, and
• the memory circuit is configured to store data stored in the latch circuit, while supply of a power supply voltage is stopped.

A semiconductor device comprising:

• a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a latch circuit, and a memory circuit,
• wherein:
• each of the first transistor, the second transistor, and the third transistor is an n-channel transistor,
• each of the fourth transistor, the fifth transistor, and the sixth transistor is a p-channel transistor,
• one of a source and a drain of the first transistor is supplied with a low power supply voltage,
• the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
• the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,
• the other of the source and the drain of the third transistor is electrically connected to the latch circuit and one of a source and a drain of the fourth transistor,
• the other of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor,
• the other of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,
• the other of the source and the drain of the sixth transistor is supplied with a high power supply voltage,
• a gate of the first transistor is electrically connected to a gate of the sixth transistor,
• a gate of the second transistor is electrically connected to a gate of the fifth transistor,
• a gate of the third transistor is electrically connected to a gate of the fourth transistor, and
• the memory circuit is configured to store data stored in the latch circuit, while supply of a power supply voltage is stopped.