US 2018/0026610 A1Published application

Latch circuitry

AssigneeNXP B.V.

InventorKristof Laszlo Blutman

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Abstract

Circuitry is configured to store data in response to a phase transition of an input clock. The circuitry uses a master-slave latch configuration. Each of the master and slave latches includes respective feedback circuits, input circuits, and selection circuits. The feedback circuits drive outputs of the respective latches to values that are responsive to data stored in the latches. The input circuits drive the output of the respective latches to values that are responsive to data on an input of the latches. The selection circuits select between the feedback and input circuits based upon the phase of a clock signal.

Claims18

Dependent claims

An apparatus comprising:

circuitry configured to store data in response to a phase transition of an input clock, the circuitry including:
a master latch including:
a master feedback circuit configured to drive an output of the master latch to a value that is responsive to data stored in the master latch;
a master input circuit configured to drive the output of the master latch to a value that is responsive to data on an input of the master latch;
and
a master selection circuit configured to:
select, in response to a first phase of the input clock, the master input circuit to drive the output of the master latch;
and
select, in response to a second phase of the input clock, the master feedback circuit to drive the output of the master latch;
and
a slave latch including:
a slave feedback circuit configured to drive an output of the slave latch to a value that is responsive to data stored in the slave latch;
a slave input circuit configured to drive the output of the slave latch to a value that is responsive to data on the output of the master latch;
and
a slave selection circuit configured to:
select, in response to the first phase of the input clock, the slave feedback circuit to drive the output of the slave latch;
and
select, in response to the second phase of the input clock, the slave input circuit to drive the output of the slave latch, wherein the master selection circuit is configured and arranged to, when the input of the master latch is a differential signal, select the master input circuit to drive the output of the master latch as a first phase of an output differential signal in response to a first phase of the differential signal, and to select the master feedback circuit to drive the output of the master latch as a second phase of the output differential signal.

15 more elements

An apparatus comprising:

circuitry configured to store data in response to a phase transition of an input clock, the circuitry including:
a master latch including:
a master feedback circuit configured to drive an output of the master latch to a value that is responsive to data stored in the master latch;
a master input circuit configured to drive the output of the master latch to a value that is responsive to data on an input of the master latch;
and
a master selection circuit configured to:
select, in response to a first phase of the input clock, the master input circuit to drive the output of the master latch;
and
select, in response to a second phase of the input clock, the master feedback circuit to drive the output of the master latch;
and
a slave latch including:
a slave feedback circuit configured to drive an output of the slave latch to a value that is responsive to data stored in the slave latch;
a slave input circuit configured to drive the output of the slave latch to a value that is responsive to data on the output of the master latch;
and
a slave selection circuit configured to:
select, in response to the first phase of the input clock, the slave feedback circuit to drive the output of the slave latch;
and
select, in response to the second phase of the input clock, the slave input circuit to drive the output of the slave latch, wherein the output of the master latch is a differential signal and slave input circuit includes:
a first pair of transistors with gates connected to a first signal of the differential signal, and
a second pair of transistors with gates connected to a second signal of the differential signal for the output of the master latch.

17 more elements

A method comprising:

operating circuitry that includes a master latch circuit and a slave latch circuit by:
enabling, in response a first clock phase of an input clock and using an master selection circuit of the master latch circuit, a master input circuit;
driving, using the enabled master input circuit, an output of the master latch circuit to a value that is responsive to data present on an input to the master latch circuit;
disabling, in response the first clock phase of the input clock and using a slave selection circuit of the slave latch circuit, a slave input circuit;
maintaining, using a slave feedback circuit of the slave latch circuit, an output of the slave latch circuit;
disabling, in response a second clock phase of the input clock and using the master selection circuit, the master input circuit;
maintaining, using a master feedback circuit of the master latch circuit, the output of the master latch circuit;
enabling, in response the second clock phase of the input clock and using the slave selection circuit, the slave input circuit;
and
driving, using the enabled slave input circuit, the output of the slave latch circuit to a value that is responsive to a value present on the output of the master latch circuit, wherein the slave selection circuit includes two transistors configured to operate as a logical equivalent of two AND logic gates providing an input to respective logic gates of the slave input circuit each of which is configured to operate as a logical equivalent of a NOR gate.

7 more elements

Dependencies are inferred from the claim text.

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Abstract