Charge pump

A charge pump circuit comprising:

• a first circuit configured to provide a first node of the charge pump circuit with a first first-voltage level or a first second-voltage level;
• a second circuit configured to provide a second node of the charge pump circuit with a second first-voltage level or a second second-voltage level;
• a first voltage transfer circuit;
• a second voltage transfer circuit coupled to the first voltage transfer circuit;
• and
• a first charge transfer circuit coupled between the first node of the charge pump circuit and the second node of the charge pump circuit,
• wherein
• the first node of the charge pump circuit is coupled to the first voltage transfer circuit,
• the second node of the charge pump circuit is coupled to the second voltage transfer circuit, and
• the first voltage transfer circuit is configured to:
• transfer an input voltage to a first node of the first voltage transfer circuit;
• and
• transfer a voltage of the first node of the first voltage transfer circuit to a first output node as a first output voltage;
• and
• the second voltage transfer circuit is configured to:
• transfer the first output voltage to a first node of the second voltage transfer circuit;
• and
• transfer a voltage of the first node of the second voltage transfer circuit to a second output node as a second output voltage greater than the first output voltage.

A method comprising:

• causing a first node and a second node to have a first high logical value;
• causing a third node and a fourth node to have a low logical value;
• causing the third node to have the first high logical value, resulting in the first node to transition from the first high logical value to a second high logical value through a first capacitive element;
• causing the second node to have the second high logical value based on the second high logical value of the first node;
• causing the third node and the fourth node to have a same voltage value about half of a voltage value of the first high logical value;
• and
• causing the fourth node to have the first high logical value, resulting in the second node transitioning from the second high logical value to a third high logical value through a second capacitive element, wherein
• a voltage value of the second high logical value is higher than a voltage value of the first high voltage value and is lower than a voltage value of the third high logical value.