Heterostructure Power Transistor with AlSiN Passivation Layer
AssigneePower Integrations, Inc.
InventorsJamal Ramdani, Michael Murphy, John Paul Edwards
Life of this patent
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Abstract
A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. An AlSiN passivation layer is disposed on the second active layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with a gate being disposed between the first and second ohmic contacts.
Claims28
A heterostructure power transistor comprising:
- a first active layer;
- a second active layer disposed above the first active layer, a two-dimensional electron gas layer forming between the first and second active layers;
- a passivation/gate dielectric layer comprising aluminum silicon nitride (AlSiN) disposed above the second active layer;
- a gate;
- a second gate dielectric layer disposed above the passivation/gate dielectric layer, the gate being disposed above the second gate dielectric layer, wherein the passivation/gate dielectric layer has a first thickness and the second gate dielectric has a second thickness;
- first and second ohmic contacts that electrically connect to the second active layer, the first and second ohmic contacts being laterally spaced-apart, the gate being disposed between the first and second ohmic contacts.
A method of fabricating a heterostructure semiconductor device comprising:
- forming a first active layer over a substrate;
- forming a second active layer above the first active layer, the first active layer and the second active layer having different bandgaps such that a two-dimensional electron gas layer is formed therebetween;
- forming passivation/gate dielectric layer comprising aluminum silicon nitride (AlSiN) above the second active layer, the passivation/gate dielectric layer having a first thickness;
- forming a second date dielectric layer above the passivation/gate dielectric layer, the second gate dielectric layer having a second thickness;
- forming first and second ohmic contacts that each extend vertically through the second gate dielectric layer and the passivation/gate dielectric layer, the first and second ohmic contacts being laterally spaced-apart and electrically connected to the second active layer;
- and
- forming a gate at a lateral position between the first and second ohmic contacts.
Dependencies are inferred from the claim text.