B-TRAN Geometry and Structure That Provides Both High Gain and High Current Density

A method for optimizing a power semiconductor device which includes:

• a first-type semiconductor die having first and second surfaces;
• first and second second-type emitter/collector regions, located respectively on the first and second;
• first and second first-type base contact regions, located respectively on the first and second surfaces;
• and first and second trenched field plate structures, which are located respectively on the first and second surfaces and abutting the first and the second emitter/collector regions respectively, and which each include a respective conductor separated from the die by a respective dielectric;
• comprising the actions of:
• adjusting the thickness of the dielectric in the trenched field plate structures to be large enough to withstand the base-to-emitter voltage, but small enough to provide good electrical coupling between the poly field plate and the adjacent semiconductor die;
• adjusting the minimum width of both of the base contact regions to be not only small enough to provide an acceptably low reverse base contact region pinch-off voltage, but also large enough to avoid degradation of base resistance;
• and adjusting the minimum width of both of the emitter/collector regions to be small enough that current density is acceptably high at the center of thereof;
• whereby, after fabrication of the resulting device, the breakdown voltage is improved under either polarity of applied voltage, degradation of base resistance is avoided, and emitter efficiency is kept acceptably high.

A power semiconductor device, comprising:

• a p-type semiconductor die having first and second surfaces;
• first and second n-type emitter/collector regions, located respectively on the first and second surface of the semiconductor die;
• first and second p-type base contact regions, located respectively on the first and second surface of the semiconductor die;
• first and second trenched field plate structures, located respectively on the first and second surface of the semiconductor die;
• wherein the first emitter/collector region is electrically connected to, and is entirely surrounded by, the first trenched field plate structure;
• wherein the second emitter/collector region is electrically connected to, and is entirely surrounded by, the second trenched field plate structure;
• wherein the dielectric thickness in the trenched field plate structures is large enough to withstand the base-to-emitter voltage, but small enough to provide good electrical coupling between the poly field plate and the adjacent p-type silicon;
• wherein the minimum width of both of the base contact regions is small enough to provide an acceptably low reverse base contact region pinch-off voltage, but large enough to avoid degradation of base resistance;
• and wherein the minimum width of both of the emitter/collector regions is small enough that current density is acceptably high at the center of thereof;
• whereby the breakdown voltage is improved under either polarity of applied voltage, degradation of base resistance is avoided, and emitter efficiency is kept acceptably high.

A power semiconductor device, comprising:

• an n-type semiconductor die having first and second surfaces;
• first and second p-type emitter/collector regions, located respectively on the first and second surface of the semiconductor die;
• first and second n-type base contact regions, located respectively on the first and second surface of the semiconductor die;
• first and second trenched field plate structures, located respectively on the first and second surface of the semiconductor die;
• wherein the first emitter/collector region is electrically connected to, and is entirely surrounded by, the first trenched field plate structure;
• wherein the second emitter/collector region is electrically connected to, and is entirely surrounded by, the second trenched field plate structure;
• wherein the dielectric thickness in the trenched field plate structures is large enough to withstand the base-to-emitter voltage, but small enough to provide good electrical coupling between the poly field plate and the adjacent p-type silicon;
• wherein the minimum width of both of the base contact regions is small enough to provide an acceptably low reverse base contact region pinch-off voltage, but large enough to avoid degradation of base resistance;
• and wherein the minimum width of both of the emitter/collector regions is small enough that current density is acceptably high at the center of thereof;
• whereby the breakdown voltage is improved under either polarity of applied voltage, degradation of base resistance is avoided, and emitter efficiency is kept acceptably high.