Semiconductor device having multiwork function gate patterns

A semiconductor device comprising:

• a semiconductor substrate having a first area in which a first NMOS transistor is formed, a second area in which a second NMOS transistor having a different threshold voltage than the first NMOS transistor is formed, a third area in which a first PMOS transistor is formed, and a fourth area in which a second PMOS transistor having a different threshold voltage from the first PMOS transistor is formed;
• and
• a first NMOS gate pattern on the first area, a second NMOS gate pattern on the second area, a first PMOS gate pattern on the third area, and a second PMOS gate pattern on the fourth area,
• wherein a first NMOS gate barrier pattern of the first NMOS gate pattern and a second NMOS gate barrier pattern of the second NMOS gate pattern include different metal materials from each other,
• a first PMOS gate barrier pattern of the first PMOS gate pattern and a second PMOS gate barrier pattern of the second PMOS gate pattern include different metal materials from each other, and
• the first, second, third and fourth areas each include an active region having a fin configured to protrude from a surface of the semiconductor substrate in a direction perpendicular to the semiconductor substrate, and the first NMOS gate pattern, the second NMOS gate pattern, the first PMOS gate pattern and the second PMOS gate pattern respectively cover an upper surface and side surfaces of the fins in the first, second, third and fourth areas.

A semiconductor device comprising:

• a semiconductor substrate including a first area having a first NMOS transistor and a second area having a second NMOS transistor that has a different threshold voltage than the first NMOS transistor;
• a first gate insulating pattern on the first area and a second gate insulating pattern on the second area;
• a first gate barrier pattern on the first gate insulating pattern and a second gate barrier pattern on the second gate insulating pattern;
• a first work function metal pattern on the first gate barrier pattern and a second work function metal pattern on the second gate barrier pattern;
• and
• a first barrier capping pattern on the first work function metal pattern and a second barrier capping pattern on the second work function pattern,
• wherein the first gate barrier pattern includes a metal material having a different work function than the second gate barrier pattern, and
• the first gate barrier pattern and the second gate barrier pattern each comprise multi-layer patterns, and a layer pattern of the first gate barrier pattern includes different metal materials than a corresponding layer pattern of the second gate barrier pattern.