Enhancement Mode Field-Effect Transistor with a Gate Dielectric Layer Recessed on a Composite Barrier Layer for High Static Performance

A pair of enhancement mode transistors comprising:

• a composite barrier layer comprising a lower barrier layer and an upper barrier layer arranged over the lower barrier layer, wherein the lower and upper barrier layers have different polarizations, wherein the composite barrier layer further comprises a first gate opening and a second gate opening, and wherein the first and second gate openings extend into the composite barrier layer to different depths;
• a channel layer arranged under the composite barrier layer, such that a heterojunction is defined at an interface between the channel layer and the composite barrier layer;
• and
• a first gate electrode and a second gate electrode respectively spaced over the first and second gate openings respectively by a first gate dielectric layer and a second gate dielectric layer, wherein the first and second gate dielectric layers are respectively arranged in the first and second gate openings and wherein the first and second gate electrodes extend to different depths beneath an uppermost surface of the lower barrier layer.

An enhancement mode transistor comprising:

• a composite barrier layer comprising a lower barrier layer and an upper barrier layer, wherein the upper barrier layer overlies and contacts the lower barrier layer, wherein the upper barrier layer has a different polarization than the lower barrier layer, and wherein the composite barrier layer further comprises a gate opening extending through the upper barrier layer to expose the lower barrier layer;
• a source electrode and a drain electrode respectively on opposite sides of the gate opening and laterally spaced from the gate opening;
• a channel layer under the composite barrier layer, such that a heterojunction is defined at an interface between the channel layer and the composite barrier layer, wherein an upper surface of the channel layer is separated from the source electrode and the drain electrode by the lower barrier layer;
• a gate dielectric layer over and contacting the lower barrier layer, wherein the gate dielectric layer contacts the lower barrier layer within the gate opening;
• and
• a gate electrode over and contacting the gate dielectric layer.