Power semiconductor device
AssigneeUniversity of Warwick
InventorsPeter Gammon, Chun Wa Chan
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Abstract
A power semiconductor device is described. The device comprises a silicon carbide substrate and a layer of monocrystalline silicon having a thickness tSi no more than 5 μm disposed directly on the substrate or directly on an interfacial layer having a thickness no more than 100 nm which is disposed directly on the substrate. The device comprises a lateral transistor, such as a laterally-diffused metal oxide semiconductor transistor or lateral insulated gate bipolar transistor, comprising first and second contacts laterally-spaced contact regions disposed in the monocrystalline silicon layer.
Claims17
1-15. (canceled)
A power semiconductor device comprising:
- a silicon carbide substrate;
- a layer of monocrystalline silicon having a thickness no more than 5 μm disposed directly on an interfacial layer having a thickness no more than 100 nm which is disposed directly on the substrate;
- and
- a lateral power transistor which is a laterally-diffused metal oxide semiconductor transistor or insulated gate bipolar transistor, the transistor comprising:
- first and second contact laterally-spaced contact regions disposed in the monocrystalline silicon layer, and
- a drift region disposed in the monocrystalline silicon layer.
Dependencies are inferred from the claim text.