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US 2018/0026076 A1Published application
High density multi-time programmable resistive memory devices and method of forming thereof
AssigneeGlobalfoundries Singapore Pte. Ltd.
InventorsXuan Anh TRAN, Eng Huat TOH
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Abstract
Multi-time programmable (MTP) random access memory (RRAM) devices and methods for forming a MTP RRAM device are disclosed. The method includes providing a substrate. The substrate is prepared with at least a first region for accommodating one or more multi-programmable based resistive random access memory (RRAM) cell. A fin-type based selector is provided over the substrate in the first region. A storage element of the RRAM cell is formed over the fin-type based selector. The fin-type based selector is coupled in series with the storage element of the RRAM cell.
Claims20
A semiconductor device comprising:
- a substrate having at least a first region for accommodating one or more multi-time programmable resistive random access memory (RRAM) cell, wherein the substrate comprises a fin structure disposed in the first region, wherein the fin structure comprises first polarity dopants;
- an isolation layer disposed on the substrate, wherein the isolation layer surrounds a bottom fin portion of the fin structure, wherein a top fin portion of the fin structure is exposed above the isolation layer;
- a first semiconductor layer disposed over the top fin portion of the fin structure, wherein the first semiconductor layer wraps around a top surface and sides of the top fin portion, and the first semiconductor layer comprises second polarity type dopants opposite to the first polarity type;
- a second semiconductor layer disposed over the first semiconductor layer in the first region, wherein the second semiconductor layer wraps around a top surface and sides of the first semiconductor layer, and the second semiconductor layer comprises the first polarity type dopants, wherein the combination of the fin structure, the first semiconductor layer and the second semiconductor layer defines a fin-type selector in the first region;
- and
- a storage element of the RRAM cell disposed over the fin-type selector, wherein the fin-type selector is coupled in series with the storage element of the RRAM cell.
3 more elements
A semiconductor device comprising:
- a substrate prepared with a memory region and a non-memory region, wherein a first fin structure is disposed in the memory region and a second fin structure is disposed in the non-memory region;
- an isolation layer disposed on a top surface of the substrate in the memory and non-memory regions, wherein the isolation layer surrounds a bottom fin portion of the first and second fin structures, and a top portion of the first and second fin structures are exposed above the isolation layer;
- a first semiconductor layer disposed over the first and second fin structures, wherein the first semiconductor layer wraps around a top surface and sides of the top fin portion of the first fin structure;
- a second semiconductor layer disposed over the first fin structure in the memory region, wherein the second semiconductor layer is disposed over the first semiconductor layer and wraps around a top surface and sides of the first semiconductor layer;
- and
- a storage element disposed over the first fin structure in the memory region, wherein the storage element is disposed above a top surface of the second semiconductor layer, and the storage element is in electrical communication with the second semiconductor layer.
3 more elements
A semiconductor device comprising:
- a substrate prepared with a memory region for accommodating one or more multi-time programmable resistive random access memory (RRAM) cell, wherein the substrate comprises a fin structure disposed in the memory region;
- a first semiconductor layer disposed on a top fin portion of the fin structure, wherein the first semiconductor layer wraps around a top surface and sides of the top fin portion, and the first semiconductor layer comprises second polarity type dopants;
- a second semiconductor layer disposed over the first semiconductor layer in the memory region, wherein the second semiconductor layer wraps around a top surface and sides of the first semiconductor layer, and the second semiconductor layer comprises first polarity type dopants;
- and
- a storage element of the RRAM cell disposed over the fin structure in the memory region, wherein the storage element is disposed above the second semiconductor layer, and the storage element is in electrical communication with the second semiconductor layer.
2 more elements
Dependencies are inferred from the claim text.