Complementary metal-oxide-semiconductor (cmos) image sensor (cis) package with an image buffer

An image sensor package comprising:

• a first integrated circuit (IC) die comprising a pixel sensor array;
• a second IC die under and bonded to the first IC die;
• and
• a fan-out structure under and bonded to the second IC die, wherein the fan-out structure comprises:
• a third IC die;
• a fan-out dielectric layer laterally adjacent to the third IC die;
• a through insulator via (TIV) extending through the fan-out dielectric layer;
• and
• one or more redistribution layers (RDLs) under the third IC die and the TIV, wherein the one or more RDLs electrically couple to the third IC die and the TIV;
• wherein the second IC die comprises:
• a semiconductor substrate along a bottom of the second IC die;
• and
• a through substrate via (TSV) extending through the semiconductor substrate, from the bottom of the second IC die, wherein the TSV is aligned and electrically coupled to the TIV.

An image sensor package comprising:

• a first integrated circuit (IC) die comprising a pixel sensor array and a first interconnect layer, wherein the first interconnect layer is electrically coupled to and underlies the pixel sensor array;
• a second IC die under the first IC die, wherein the second IC die is bonded and electrically coupled to the first IC die, and wherein the second IC die comprises:
• a semiconductor substrate along a bottom of the second IC die;
• and
• a pair of through substrate vias (TSVs) extending through the semiconductor substrate from the bottom of the second IC die;
• and
• a fan-out structure under and bonded to the second IC die, wherein the fan-out structure comprises:
• a fan-out dielectric layer;
• a third IC die over the fan-out dielectric layer, wherein the third IC die is recessed into the fan-out dielectric layer such that a top surface of the third IC die is even with a top surface of the fan-out dielectric layer;
• a pair of through insulator vias (TIV) extending through the fan-out dielectric layer, wherein the TIVs are on opposite sides of the third IC die, and wherein the TIVs are aligned and electrically coupled to the TSVs, respectively;
• and
• one or more redistribution layers (RDLs) under the third IC die and the TIVs, wherein the one or more RDLs electrically couple to the third IC die and the TIVs.