US 2018/0026024 A1 · SEMICONDUCTOR DEVICE

Abstract

An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.

Claims15

Dependent claims

(canceled)

A semiconductor device comprising:

a first inverter;
and
a second inverter connected to the first inverter in series, wherein:
the first inverter comprises a first p-channel transistor and a first n-channel transistor;
the second inverter comprises a second p-channel transistor and a second n-channel transistor;
the first p-channel transistor comprises a first source and a first drain formed in a first projection semiconductor layer extending along a first direction, and a first gate formed by a first gate wiring extending along a second direction perpendicular to the first direction such that the first source of the first p-channel transistor is coupled with a first local connection wiring extending along the second direction and the first drain of the first p-channel transistor is coupled with a second local connection wiring extending along the second direction;
the first gate wiring is arranged between the first local connection wiring and the second local connection wiring in plan view;
the first n-channel transistor comprises a second source and a second drain formed in a second projection semiconductor layers extending along the first direction, and a second gate formed by the first gate wiring such that the second source of the first n-channel transistor is coupled with a third local connection wiring extending along the second direction and the second drain of the first n-channel transistor is coupled with a fourth local connection wiring extending along the second direction;
the first gate wiring is arranged between the third local connection wiring and the fourth local connection wiring in plan view;
the second p-channel transistor comprises a third source and a third drain formed in a third projection semiconductor layer extending along the first direction, and a third gate formed by a second gate wiring extending along the second direction such that the third source of the second p-channel transistor is coupled with a fifth local connection wiring extending along the second direction and the third drain of the second p-channel transistor is coupled with a sixth local connection wiring extending along the second direction;
the second gate wiring is arranged between the fifth local connection wiring and the sixth local connection wiring in plan view;
the second n-channel transistor comprises a fourth source and a fourth drain formed in a fourth projection semiconductor layer extending along the first direction, and a fourth gate formed by the second gate wiring such that the forth source of the second n-channel transistor is coupled with a seventh local connection wiring extending along the second direction and the forth drain of the second n-channel transistor is coupled with an eighth local connection wiring extending along the second direction;
the second gate wiring is arranged between the seventh local connection wiring and the eighth local connection wiring in plan view;
the first and fourth local connection wirings are coupled with the second gate wiring via a ninth local connection wiring extending along the second direction;
a dummy gate wiring extends along the second direction and is arranged adjacent to the first, fourth and ninth local connection wirings such that the dummy gate wiring is arranged between the first local connection wiring and the ninth local connection wiring and between the fourth local connection wiring and the ninth local connection wiring;
the first local connection wiring is coupled with the ninth local connection wiring via a tenth local connection wiring overlapping with the dummy gate wiring;
the fourth local connection wiring is coupled with the ninth local connection wiring via an eleventh connection wiring overlapping with the dummy gate wiring;
and
the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh local wirings are formed in a first insulating layer.

16 more elements

A semiconductor device comprising:

a first inverter;
and
a second inverter connected to the first inverter in series, wherein:
the first inverter comprises a first p-channel transistor and a first n-channel transistor;
the second inverter comprises a second p-channel transistor and a second n-channel transistor;
the first p-channel transistor comprises a first source and a first drain formed in a first projection semiconductor layer extending along a first direction, and a first gate formed by a first gate wiring extending along a second direction perpendicular to the first direction such that the first source of the first p-channel transistor is coupled with a first local connection wiring extending along the second direction and the first drain of the first p-channel transistor is coupled with a second local connection wiring extending along the second direction;
the first gate wiring is arranged between the first local connection wiring and the second local connection wiring in plan view;
the first n-channel transistor comprises a second source and a second drain formed in a second projection semiconductor layers extending along the first direction, and a second gate formed by the first gate wiring such that the second source of the first n-channel transistor is coupled with a third local connection wiring extending along the second direction and the second drain of the first n-channel transistor is coupled with a fourth local connection wiring extending along the second direction;
the first gate wiring is arranged between the third local connection wiring and the fourth local connection wiring in plan view;
the second p-channel transistor comprises a third source and a third drain formed in a third projection semiconductor layer extending along the first direction, and a third gate formed by a second gate wiring extending along the second direction such that the third source of the second p-channel transistor is coupled with a fifth local connection wiring extending along the second direction and the third drain of the second p-channel transistor is coupled with a sixth local connection wiring extending along the second direction;
the second gate wiring is arranged between the fifth local connection wiring and the sixth local connection wiring in plan view;
the second n-channel transistor comprises a fourth source and a fourth drain formed in a fourth projection semiconductor layer extending along the first direction, and a fourth gate formed by the second gate wiring such that the forth source of the second n-channel transistor is coupled with a seventh local connection wiring extending along the second direction and the forth drain of the second n-channel transistor is coupled with an eighth local connection wiring extending along the second direction;
the second gate wiring is arranged between the seventh local connection wiring and the eighth local connection wiring in plan view;
the first and fourth local connection wirings are coupled with the second gate wiring via a ninth local connection wiring extending along the second direction;
a dummy gate wiring extends along the second direction and is arranged adjacent to the first, fourth and ninth local connection wirings such that the dummy gate wiring is arranged between the first local connection wiring and the ninth local connection wiring and between the fourth local connection wiring and the ninth local connection wiring;
the first local connection wiring is coupled with the ninth local connection wiring via a tenth local connection wiring overlapping with the dummy gate wiring;
the fourth local connection wiring is coupled with the ninth local connection wiring via an eleventh connection wiring overlapping with the dummy gate wiring;
and
the tenth local and eleventh connection wirings are directly in contact with the dummy gate wiring;

16 more elements

Dependencies are inferred from the claim text.

Facts

Application

15/719,830Filed 29 Sep 2017

Priority

JP 2014-16615718 Aug 2014

Published

25 Jan 2018

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10D 89/10
Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00: integrated device layouts
G06F 30/394
Circuit design at the physical level: routing
H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]
H10D 84/853
Complementary IGFETs, e.g. CMOS: comprising FinFETs

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Abstract

Claims15