Package-on-Package Devices with Multiple Levels and Methods Therefor

A method for forming a package-on-package device, comprising:

• obtaining a package substrate;
• first surface mount interconnecting a first integrated circuit die to an upper surface of the package substrate;
• coupling first conductive lines to the upper surface of the package substrate, the first conductive lines extending away from the upper surface of the package substrate to terminate at a first height;
• coupling second conductive lines to the upper surface of the package substrate, the second conductive lines extending away from the upper surface of the package substrate to terminate at a second height greater than the first height;
• the first conductive lines and the second conductive lines located in a fan-out region;
• forming a first molding layer over the upper surface of the package substrate, around sidewall surfaces of the first integrated circuit die, and around bases and shafts of the first conductive lines and the second conductive lines;
• second surface mount interconnecting a first wafer-level packaged microelectronic component and a second wafer-level packaged microelectronic component above an upper surface of the first molding layer, the second surface mount interconnecting including coupling a first and a second set of upper portions of the first conductive lines respectively to the first wafer-level packaged microelectronic component and the second wafer-level packaged microelectronic component;
• and
• third surface mount interconnecting a third wafer-level packaged microelectronic component and a fourth wafer-level packaged microelectronic component above the first and the second wafer-level packaged microelectronic components, the third surface mount interconnecting including coupling a first and a second set of upper portions of the second conductive lines respectively to the third wafer-level packaged microelectronic component and the fourth wafer-level packaged microelectronic component.