Back to results
US 2018/0025995 A1Published application
Reducing wafer warpage during wafer processing
AssigneeToshiba Memory Corporation
InventorKenji KONOMI
Life of this patent
Estimating the term…
Abstract
According to one embodiment, there is provided a manufacturing method of a semiconductor device. The method includes forming a first guard ring around a first chip region on a semiconductor wafer. The method includes forming a second guard ring around a second chip region on the semiconductor wafer. The method includes mechanically connecting the first guard ring with the second guard ring through a joist structure.
Claims11
1:
- A manufacturing method of a semiconductor device comprising:
- forming a first guard ring around a first chip region on a semiconductor wafer;
- forming a second guard ring around a second chip region on the semiconductor wafer;
- and
- mechanically connecting the first guard ring with the second guard ring through a joist structure.
2 more elements
2:
- The manufacturing method of the semiconductor device according to claim 1,
- wherein the connecting through the joist structure further comprises connecting a first portion with a second portion through a number of connection patterns, the first portion being a portion extending along the second guard ring in the first guard ring, the second portion being a portion extending along the first guard ring.
3:
- The manufacturing method of the semiconductor device according to claim 2,
- wherein a number of the connection patterns are formed of a material having a tensile stress or a compressive stress according to a warping state of the semiconductor wafer.
4:
- The manufacturing method of the semiconductor device according to claim 2,
- wherein the connecting through the joist structure further comprises connecting the first portion with the second portion through a number of the connection patterns not to overlap a mark pattern arranged between the first portion and the second portion.
5:
- The manufacturing method of the semiconductor device according to claim 2,
- wherein the connecting through the joist structure further comprises
- connecting one end side of the first portion with one end side of the second portion through a first connection pattern,
- connecting another end side of the first portion with another end side of the second portion through a second connection pattern, and
- connecting the first portion with the second portion through a third connection pattern between the first connection pattern and the second connection pattern.
2 more elements
6:
- The manufacturing method of the semiconductor device according to claim 5,
- wherein each of the first connection pattern, the second connection pattern, and the third connection pattern extends obliquely to a longitudinal direction of the first portion.
7:
- The manufacturing method of the semiconductor device according to claim 5,
- wherein the connecting through the joist structure further comprises
- connecting the one end side of the first portion with the one end side of the second portion through a fourth connection pattern to intersect with the first connection pattern,
- connecting the other end side of the first portion with the other end side of the second portion through a fifth connection pattern to intersect with the second connection pattern, and
- connecting the first portion with the second portion through a sixth connection pattern between the first connection pattern and the second connection pattern to intersect with the third connection pattern.
2 more elements
8:
- The manufacturing method of the semiconductor device according to claim 7,
- wherein the first connection pattern and the fourth connection pattern form substantially a letter X shape at a planar view,
- the second connection pattern and the fifth connection pattern form substantially a letter X shape at a planar view, and
- the third connection pattern and the sixth connection pattern form substantially a letter X shape at a planar view.
1 more element
9:
- The manufacturing method of the semiconductor device according to claim 5,
- wherein an interval between the first connection pattern and the third connection pattern in a longitudinal direction of the first portion is equivalent to an interval between the third connection pattern and the second connection pattern in the longitudinal direction of the first portion.
10:
- The manufacturing method of the semiconductor device according to claim 5,
- wherein the joist structure is formed to have a same layer structure as the guard ring.
11-20. (canceled)