Semiconductor package structure and manufacturing method thereof

2:

• The semiconductor package structure of claim 1, further comprising a circuit board disposed over the second surface of the redistribution layer, and a plurality of external connectors disposed between the second surface and the circuit board to electrically connect the redistribution layer with the circuit board.

3:

• The semiconductor package structure of claim 1, further comprising a package disposed over the encapsulant and electrically connected to the redistribution layer through the interconnecting bumps.

4:

• The semiconductor package structure of claim 1, wherein each of the plurality of interconnecting bumps is a solder ball, and two opposite terminals of each of the plurality of interconnecting bumps are exposed from the encapsulant.

5:

• The semiconductor package structure of claim 1, wherein the chip comprises an active device chip and a passive device chip.

(canceled)

8:

• The semiconductor package structure of claim 7, further comprising a circuit board disposed over the fourth surface of the second redistribution layer, and a plurality of external connectors disposed between the fourth surface and the circuit board to electrically connect the second redistribution layer with the circuit board.

9:

• The semiconductor package structure of claim 7, further comprising a package disposed over the first encapsulant and electrically connected to the first redistribution layer through the first interconnecting bumps.

10:

• The semiconductor package structure of claim 7, wherein each of the plurality of first interconnecting bumps is a solder ball, and two opposite terminals of each of the plurality of first interconnecting bumps are exposed from the first encapsulant.

11:

• The semiconductor package structure of claim 7, wherein each of the plurality of second interconnecting bumps is a solder ball, and two opposite terminals of each of the plurality of second interconnecting bumps are exposed from the second encapsulant.

12:

• The semiconductor package structure of claim 7, further comprising a plurality of conductive posts disposed in the second encapsulant, wherein each of the plurality of conductive posts is a solder paste, one terminal of each of the plurality of conductive posts is connected to the second redistribution layer, and the other terminal of each of the plurality of conductive posts is connected to the corresponding second interconnecting bump.

13:

• The semiconductor package structure of claim 7, wherein the first chip comprises a memory chip and a passive device chip.

14:

• The semiconductor package structure of claim 7, wherein the second chip comprises an active device chip and a passive device chip.

15:

• The semiconductor package structure of claim 7, further comprising a third chip disposed over the fourth surface and electrically connected to the second redistribution layer.

16-20. (canceled)

22:

• The semiconductor package structure of claim 21, further comprising a circuit board disposed over the second surface of the redistribution layer, and a plurality of external connectors disposed between the second surface and the circuit board to electrically connect the redistribution layer with the circuit board.

23:

• The semiconductor package structure of claim 21, further comprising a package disposed over the encapsulant and electrically connected to the redistribution layer through the interconnecting bumps and the conductive posts.

24:

• The semiconductor package structure of claim 21, wherein the chip comprises an active device chip and a passive device chip.

25:

• The semiconductor package structure of claim 21, further comprising a second chip disposed over the second surface and electrically connected to the redistribution layer.

26:

• The semiconductor package structure of claim 1, further comprising a second redistribution layer over the second surface of the redistribution layer, wherein the second redistribution layer has a third surface and a fourth surface opposite to each other, the third surface faces the second surface, and the second chip includes a plurality of contact pads facing the third surface of the second redistribution layer.