Wafer-Level Packaged Components and Methods Therefor

A method for forming a wafer-level packaged microelectronic component, comprising:

• obtaining an integrated circuit die of a wafer having first contacts in an inner third region of a surface of the integrated circuit die;
• wafer-level processing to form a first redistribution layer on the surface of the integrated circuit die, the first redistribution layer formed to have:
• second contacts in an inner third region of a first surface of the first redistribution layer interconnected to the first contacts of the integrated circuit die with the surface of the integrated circuit die face-to-face with the first surface of the first redistribution layer;
• third contacts in an outer third region of a second surface of the first redistribution layer opposite the first surface thereof coupled for electrical conductivity to the second contacts;
• and
• the third contacts offset from the second contacts for being positioned in a fan-out region for association at least with the outer third region of the second surface of the first redistribution layer, the third contacts being surface mount contacts;
• and
• wafer-level processing to form a second redistribution layer having fourth contacts in an inner third region of a first surface of the second redistribution layer and interconnects in an outer third region of a second surface of the second redistribution layer opposite the first surface thereof.

A method for forming a wafer-level packaged microelectronic component, comprising:

• obtaining an integrated circuit die of a wafer having first contacts in an inner third region of a first surface of the integrated circuit die;
• wafer-level processing to form a first redistribution layer on the first surface of the integrated circuit die, the first redistribution layer formed to have:
• second contacts in an inner third region of a first surface of the first redistribution layer interconnected to the first contacts of the integrated circuit die with the first surface of the integrated circuit die face-to-face with the first surface of the first redistribution layer;
• third contacts in an outer third region of a second surface of the first redistribution layer opposite the first surface thereof coupled for electrical conductivity to the second contacts;
• and
• the third contacts offset from the second contacts for being positioned in a fan-out region for association at least with the outer third region of the second surface of the first redistribution layer, the third contacts being surface mount contacts;
• wafer-level processing to form a second redistribution layer on a second surface of the integrated circuit die opposite the first surface thereof, the second redistribution layer formed to have fourth contacts in an inner third region of a first surface of the second redistribution layer and interconnects in an outer third region of a second surface of the second redistribution layer opposite the first surface thereof;
• the integrated circuit die having through die vias in an outer third region of the first surface and a second surface opposite the first surface;
• the interconnects of the second redistribution layer coupled for electrical conductivity to the through die vias of the integrated circuit die with the second surface of the integrated circuit die face-to-face with the second surface of the second redistribution layer;
• and
• the interconnects offset from the fourth contacts for being positioned in the fan-out region for association at least with the outer third region of the second surface of the second redistribution layer.

A wafer-level packaged microelectronic component, comprising:

• an integrated circuit die of a wafer having first contacts in an inner third region of a first surface of the integrated circuit die and through die vias in an outer third region of the first surface of the integrated circuit die;
• a first redistribution layer having second contacts in an inner third region of a first surface of the first redistribution layer and first interconnects in an outer third region of a second surface of the first redistribution layer opposite the first surface thereof;
• the first interconnects of the first redistribution layer coupled for electrical conductivity to the through substrate vias of the integrated circuit die with a second surface of the integrated circuit die opposite the first surface thereof face-to-face with the second surface of the first redistribution layer;
• a second redistribution layer having third contacts in an inner third region of a first surface of the second redistribution layer and second interconnects in an outer third region of a second surface of the second redistribution layer opposite the first surface thereof;
• and
• the second contacts offset from the first interconnects for being positioned in a fan-out region for association at least with the outer third region of the second surface of the first redistribution layer, the second contacts being surface mount contacts.

A method for forming a wafer-level packaged microelectronic component, comprising:

• obtaining an integrated circuit die of a wafer having first contacts in an inner third region of a first surface of the integrated circuit die and through die vias in an outer third region of the first surface of the integrated circuit die;
• and
• wafer-level processing to form a first redistribution layer on the first surface of the integrated circuit die, the first redistribution layer formed to have:
• second contacts in an inner third region of a first surface of the first redistribution layer and first interconnects in an outer third region of a second surface of the first redistribution layer opposite the first surface thereof;
• the first interconnects of the first redistribution layer coupled for electrical conductivity to the through substrate vias of the integrated circuit die with a second surface of the integrated circuit die opposite the first surface thereof face-to-face with the second surface of the first redistribution layer;
• and
• the second contacts offset from the first interconnects for being positioned in a fan-out region for association at least with the outer third region of the second surface of the first redistribution layer, the second contacts being surface mount contacts;
• and
• wafer-level processing to form a second redistribution layer having third contacts in an inner third region of a first surface of the second redistribution layer and second interconnects in an outer third region of a second surface of the second redistribution layer opposite the first surface thereof.