Method of measuring misalignment of chips, a method of fabricating a fan-out panel level package using the same, and a fan-out panel level package fabricated thereby

A method of fabricating a package, comprising:

• forming cavities in a substrate;
• applying an adhesive tape to the substrate;
• providing chips in the cavity and on the adhesive tape, the chips being arranged in first and second directions in the substrate, the chips including first to n-th chips arranged in the first direction or the second direction;
• forming an encapsulation layer on the substrate, the chips, and the adhesive tape;
• removing the adhesive tape;
• and
• measuring misalignments of the chips with respect to the substrate, the measuring the misalignments of the chips including,
• obtaining images by scanning the substrate and chips provided in the substrate,
• obtaining absolute offsets of reference chips with respect to the substrate in the images, the reference chips corresponding to k-th ones of the chips in the images and k being an integer greater than or equal to 1 and less than or equal to n,
• obtaining relative offsets of subordinate chips with respect to the reference chips in the images, the subordinate chips corresponding to the chips that are not reference chips among the chips, and
• calculating misalignments of the chips based on the absolute offsets and the relative offsets.

A method of measuring misalignment of chips in a substrate, comprising:

• obtaining an image of the chips on the substrate, the chips being spaced apart from each other in rows and columns in the substrate, the chips including chip alignment marks, the substrate including substrate alignment marks corresponding to the chip alignment marks;
• obtaining absolute vertical offsets of traverse reference chips with respect to the substrate in the images, the traverse reference chips corresponding to a selected chip from each of the rows of chips, the absolute vertical offsets being based on vertical distance reference values and distances between the chip alignment marks of the traverse reference chips and the substrate alignment marks that are adjacent to the chip alignment marks of the traverse reference chips;
• obtaining relative vertical offsets of first subordinate reference chips with respect to the traverse reference chips in the images, the first subordinate chips corresponding to unselected chips from each of the rows of chips, the relative vertical offsets being based on distances between the chip alignment marks of the traverse reference chips and the chip alignment marks of the first subordinate chips that are adjacent to the chip alignment marks of the traverse reference chips;
• obtaining absolute horizontal offsets of longitudinal reference chips with respect to the substrate in the images, the longitudinal reference chips corresponding to a selected chip from each of the columns of chips, the absolute horizontal offsets being based on horizontal distance reference values and distances between the chip alignment marks of the longitudinal reference chips and the substrate alignment marks that are adjacent to the chip alignment marks of the longitudinal reference chips;
• obtaining relative horizontal offsets of second subordinate reference chips with respect to the longitudinal reference chips in the images, the second subordinate chips corresponding to unselected chips from each of the columns of chips, the horizontal vertical offsets being based on the absolute horizontal offsets and distances between the chip alignment marks of the longitudinal reference chips and the chip alignment marks of the second subordinate chips that are adjacent to the chip alignment marks of the longitudinal reference chips;
• and
• calculating misalignments of the chips based on the absolute vertical offsets, absolute horizontal offsets, relative vertical offsets, and relative horizontal offsets.