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US 2018/0025787 A1Published application
Automatic test-pattern generation for memory-shadow-logic testing
AssigneeSTMicroelectronics International N.V.
InventorNishu Kohli
Life of this patent
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Abstract
An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.
Claims20
A method, comprising:
- activating a first test memory cell and a second test memory cell during a test mode;
- causing a first logic value to be stored in the first test memory cell and causing a second logic value to be stored in the second test memory cell;
- deactivating a data-storage memory cell during the test mode;
- generating a test pattern on the first and second test memory cells such that the first test memory cell includes a first logic value and the second test memory cell includes a second logic value different from the first logic value;
- causing the first test memory cell to change a signal on a bit line from the first logic value to the second logic value;
- and
- coupling the bit line to a sense amplifier after the signal on the bit line has the second logic value.
4 more elements
A memory, comprising:
- a memory array having rows of memory cells used for data storage and an additional row of memory cells used for programming;
- wherein the additional row of memory cells includes first and second columns;
- circuitry configured to store a first logic value in the memory cell of the first column and to store a second logic value different than the first logic value in the memory cell of the second column;
- a first precharge circuit coupled to the first column;
- a second precharge circuit coupled to the second column;
- a first column multiplexer coupled to the first precharge circuit;
- a second column multiplexer coupled to the second precharge circuit;
- a first sense amplifier coupled to the first column multiplexer;
- a second sense amplifier coupled to the second column multiplexer;
- selection circuitry configured to control the first and second column multiplexers so as to select a first voltage differential corresponding to a first desired logic value to be coupled to the first sense amplifier and to select a second voltage differential corresponding to a second desired logic value to be coupled to the second sense amplifier.
7 more elements
An electronic device, comprising:
- a first test memory array located in a test row and having first bit columns;
- a second test memory array located in the test row and having second bit columns;
- a data-storage memory array located in the data row;
- a test circuit configured to enable the first test memory array and the second test memory array, and to disable the data-storage memory array, during a test mode;
- and
- wherein the test circuit is configured to select a first signal stored in the first test memory array for passage to a sense amplifier based upon a selection control signal having a first logic value matching a logic value of the first signal, and to select a second signal stored in the second test memory array for passage to the sense amplifier based upon the selection control signal having a second logic value matching a logic value of the second signal.
3 more elements
Dependencies are inferred from the claim text.