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US 2018/0025783 A1Published application
Non-volatile memory device and method of fabricating the same
AssigneesSK hynix Inc., Sogang University Research Foundation
InventorWoo Young CHOI
Life of this patent
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Abstract
Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory includes a channel layer; a data storage layer disposed on the channel layer; a plurality of control gates arranged on the data storage layer and spaced apart from one another; and one or more sub-gates, at least one of the sub-gates being arranged between two adjacent control gates.
Claims19
A non-volatile memory device, comprising:
- a channel layer;
- a data storage layer disposed on the channel layer;
- a plurality of control gates arranged on the data storage layer and spaced apart from one another;
- and
- one or more sub-gates, at least one of the sub-gates being arranged between two adjacent control gates.
2 more elements
A non-volatile memory device, comprising:
- memory cell strings, each memory cell string comprising a plurality of memory cells connected to one another in series;
- wordlines connected to control gates of the plurality of memory cells, respectively;
- sub-wordlines, at least one of the sub-wordlines being arranged between two adjacent wordlines;
- bitlines connected to first ends of the memory cell strings, respectively;
- a row decoder electrically connected to the plurality of memory cells via the wordlines and the sub-wordlines;
- and
- a column decoder electrically connected to the memory cell strings via the bitlines.
4 more elements
A method of fabricating a non-volatile memory device, the method comprising:
- forming a stacked structure by alternately and repeatedly forming one or more insulation layers and a plurality of conductive layers on a substrate, wherein the plurality of conductive layers comprise first conductive layers for forming control gates and second conductive layers for forming sub-gates, at least one of the sub-gates being formed between two adjacent control gates;
- forming via holes extending in a vertical direction that is normal to a main surface of the substrate by patterning the stacked structure;
- forming a data storage layer on a sidewall of each of the via holes;
- and
- forming a semiconductor pillar comprising a channel layer in a groove region defined by the data storage layer in each of the via holes.
2 more elements
Dependencies are inferred from the claim text.