Non-volatile memory device

Abstract

A non-volatile memory device of the present disclosure includes: a plurality of bit lines; a plurality of word lines; a memory cell array having a plurality of memory cells each including a non-volatile storage element and being disposed at crossing sections of the bit lines and the word lines; a reference voltage generator circuit that generates a readout reference voltage serving as a reference for discrimination of data values stored on the memory cells; a readout circuit that reads the data values stored on the memory cells by detecting values of readout voltages from the memory cells relative to the readout reference voltage in a state where a predetermined current-limited readout current is applied to the bit lines; and an address compensation circuit that changes the readout reference voltage in accordance with a placement position of a memory cell to be read of the memory cells in the readout circuit.

Dependencies are inferred from the claim text.