Semiconductor devices having a refresh operation

A semiconductor device comprising:

• a first row address generation circuit configured to generate a first row address for refreshing memory cells connected to first group word lines included in a first up block and a second up block from a refresh command and an active signal in response to a period selection signal and a first period signal;
• a second row address generation circuit configured to generate a second row address for refreshing memory cells connected to second group word lines included in a first down block and a second down block from the refresh command and the active signal in response to the period selection signal and a second period signal;
• and
• a period signal generation circuit configured to generate the first period signal, the second period signal and the period selection signal in response to a first start signal, a first end signal, a second start signal and a second end signal.